The Fetch-Decode-Execute Cycle

Watch how the CPU processes the instruction LOAD 5 step by step

⚙ FETCH

Step 1/12

Speed: 1.5s

CPU

Program Counter (PC)

-

Current Instruction Reg (CIR)

-

Memory Address Reg (MAR)

-

Memory Data Reg (MDR)

-

Accumulator (ACC)

0

Control Unit (CU)

Idle

↔ Address Bus ↔ Data Bus

RAM

Address 5: 42

Address 100: LOAD 5

Address 101: ADD 3

Address 102: STORE 8